VHDL: Code to put a numeric value in a STD_LOGIC_VECTOR variable -



VHDL: Code to put a numeric value in a STD_LOGIC_VECTOR variable -

i come in number in a variable of type std_logic_vector have problems compiler.

signal cl_output_cha : std_logic_vector (16-1 downto 0); cl_ouput_cha <= 111111111111111;

the compiler give me these 2 messages:

the integer value of 111111111111111 greater integer'high. type of cl_output_cha incompatible type of 111111111111111.

could give me proper code line set in variable particular numeric value? give thanks much.

first of all, error because number have written treated integer.

i take mean number binary? in case utilize "".

cl_ouput_cha <= "111111111111111";

you can go hex, x"".

cl_ouput_cha <= x"ffff";

if want assign integer std_logic_vector, can this.

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.numeric_std.all; ... cl_ouput_cha <= std_logic_vector(to_unsigned(12345, ch1_ouput_cha'length)); -- natural cl_ouput_cha <= std_logic_vector(to_signed(12345, ch1_ouput_cha'length)); -- signed

where 12345 integer (or natural) , 16 width.

vhdl numeric

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